Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions

As IC fabrication capabilities ex tend down to sub half micron the signi cance of interconnect delay and power dissipation can no longer be ignored Existing enhancements to synthesis and physical design tools have not been able to solve the problem The only re maining alternative is that tradeo s in logical and physical domains must be addressed in an integrated manner Vast business opportunities will be lost unless more revolutionary changes to design ow are made This paper discusses three technologies which are key to perform ing logic synthesis and physical layout optimiza tion in tandem They are early oorplanning layout driven logic synthesis and post layout